One aspect relates to a connecting structure for an electronic device, and to a connecting structure for a semiconductor device including a trench structure, such as a vertical trench field-effect transistor, or trench-gate transistor, a trench capacitor, or trench capacitance, or a DMOS (double diffused metal oxide semiconductor) power transistor comprising a respective trench structure.
In many modern devices, including semiconductor devices, the construction space available for a specific device is a set constraint in the context of developing such devices. Especially with small semiconductor devices having typical chip edge lengths of 2 mm and less, the surface area which has to be provided for contacting the finished device represents a substantial proportion of the overall surface area of the device. In this context, bondpads frequently need to include a surface area of up to 500 μm×500 μm, for example to enable, in the context of a common bond processing step, contacting between the respective bondpad and the housing via more than one bondwire, or contact wire.
Even in the case of other contacting methods, for example by means of pressing contacts or resilient pins, the respective contacting area cannot be designed to be significantly smaller. If, typically, for example, three bondwires having diameters of 50 to 100 μm in each case are used per bondpad, the respective bondpad may hardly be designed to be smaller than 300 μm×300 μm. Also, there are conductor-line structures on the semiconductor device which are for electrically contacting the semiconducting structures and cells. In the context of development, the surface area necessary for this is not available, or is available only to a highly limited extent, for the actual cell structure of the semiconducting device.
The connecting structures for operation thus considerably restrict the surface area available for the cell structure of the semiconducting device. With regard to the overall surface area of the device, the space requirements of the contacting connecting structures considerably reduce the possible space requirements or the possible surface area for the active regions. The construction space necessary for contacting thus considerably restricts the efficient further development of the devices.
When developing new generations of DMOS power transistors, an important goal is the reduction of the specific on-resistance Ron·A, for example. A reduction of the specific on-resistance is desirable for the very reason alone that it may minimize the static power loss, on the one hand, and that higher current densities may be achieved, on the other hand, as a result of which smaller and cheaper chips may be employed for the same total current.